Hardware-Enabled Sovereignty: Securing Military Systems Through a Novel and Resilient Defense Architecture
In: 2026 18th International Conference on Cyber Conflict (CyCon)
doi.org/10.23919/CyCon70911.2026.11609427
Unified cyber actions between nations need every partnerâs cyber-capabilities to hold under stress. A partnerâs cyber-capabilities hold only if its systems are sovereign. Digital sovereignty should guarantee this. But it has no structural definition yet. Even existing policies mandate digital sovereignty without the possibility to measure or enforce it. A mandate says the system must stay operational when its vendor pulls out, but the system cannot. Procurement buys a national system that still runs on foreign silicon or stores data in another jurisdiction. We call this gap the empty mandate. We propose the Sovereignty Architecture Framework (SAF) that defines digital sovereignty structurally, as a relation between a governor and a system. Governors are states, organizations, or individuals. Each holds scoped authority over a layered capability base that governance can draw on but never substitute. We describe a system's sovereignty through four capability classes, Control, Continuity, Transparency, and Independency. We assess it across the systemâs architectural layers, bounded by the weakest system in the path. We apply the framework to a naval combat management system developed for research. We lay out the system in two matrices sharing one coordinate system. The assessment matrix makes every cell a checkable fact, the design matrix every cell a design-time mandate, and a per-cell dial with enforce, compensate, or accept sets how far it is pushed. We classify each unmet mandate as an unintended failure, a deliberate in-scope decision, or an out-of-scope authorization violation. We show that this framework makes sovereignty measurable and designable. It keeps an assessment honest by keeping accepted gaps, failures, and authorization violations distinct. It grounds justified trust in the assessed state of each capability class. Because a partnerâs cyber-capabilities rest on the assessed state of the capability classes in its systems, a coordinated response is only as durable as the weakest partnerâs capability base.
Trustworthiness by Structural Elimination
In: 29th Forum on Specification and Design Languages
Typically, developers achieve hardware trustworthiness by adding security modules, redundancy, or verification engines, increasing area requirements, energy consumption, and complexity. We propose trustworthiness by structural elimination, generating hardware directly from application code so that only required functionality exists physically. Our methodology eliminates unused code paths to produce a minimal, correct architecture, achieving correctness, reliability, security, and energy efficiency simultaneously without additive components.
SOVEREIGN - Towards a Holistic Approach to Critical Infrastructure Protection
In: Proceedings of the 19th International Conference on Availability, Reliability and Security
doi.org/10.1145/3664476.3671410
In the digital age, cyber-threats are a growing concern for individuals, businesses, and governments alike. These threats can range from data breaches and identity theft to large-scale attacks on critical infrastructure. The consequences of such attacks can be severe, leading to financial losses, threats to national security, and the loss of lives. This paper presents a holistic approach to increase the security of critical infrastructures. For that, we propose an open, self-configurable, and AI-based automated cyber-defense platform that runs on specifically hardened devices and own hardware, can be deeply embedded in critical infrastructures and provides full visibility on network, endpoints, and software. In this paper, starting from a thorough analysis of related work, we describe the vision of our SOVEREIGN platform in the form of an architecture, discuss individual building blocks, and evaluate it qualitatively with respect to our requirements.
A Modern Approach to Application Specific Processors for Improving the Security of Embedded Devices
In: IECON 2021-47rd Annual Conference of the IEEE Industrial Electronics Society
doi.org/10.1109/iecon48115.2021.9589730
The security of embedded devices is very important today because critical infrastructures like medical devices, transportation, communication, and smart grids deploy them in large numbers. In all of these areas cybersecurity is the enabler for safety as failing or compromised devices threaten the life of people. Often, it is not feasible securing already deployed devices because of high costs, missing physical access, or defective hardware. Therefore, the next generation devices deployed in the future have to be more secure and more resilient to cyber attacks. This paper proposes a new approach to secure these next generation devices by using program optimized Application Specific Processors (ASPs) and employing an easy to integrate development flow for embedded developers. It evaluates the security improvement by analyzing the vulnerability of the approach against typical attack patterns.
HDL FSM Code Generation Using a MIPS-based Assembler
In: 2019 IEEE 28th International Symposium on Industrial Electronics (ISIE)
doi.org/10.1109/isie.2019.8781095
The implementation of Finite State Machines (FSMs) is a recurring task in the development of embedded systems when Field Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASICs) are being designed. The standard implementation language for these FSMs in this context is a Hardware Description Language (HDL) like VHDL or Verilog. The implementation complexity can rise quickly depending on FSM size and which devices/components are controlled. In many cases FSMs enforce sequential execution of instructions in the concurrent world of FPGAs or ASICs. This paper proposes the use of a MIPS-based assembly dialect and assembler called aFSM to decrease the implementation complexity of such FSMs by automatically generating the FSMs VHDL code. A human VHDL implementation of an Ethernet controller with an FPGA is compared against the implementation with aFSM to evaluate the assembler.